1. Field of the Invention
The present invention relates to a high-speed output circuit disposed on a periphery of a semiconductor integrated circuit, the output circuit interfacing between the semiconductor integrated circuit and an external circuitry or a system bus supposed to be connected to the semiconductor integrated circuit. The high-speed output circuit is well suited for a high speed semiconductor integrated circuit, such as an SRAM, composing a computer system. In particular, the present invention relates to a technique of matching the impedance of an output buffer in the output circuit on a large scale integrated circuit (LSI) with the impedance of the external circuitry or the system bus in the computer system.
2. Description of the Prior Art
LSI chips installed in a computer system are connected to a system bus of the computer system through respective output circuits disposed on the periphery of the LSI chips. As the interface circuit, a small signal amplitude interface circuit, for example, a high-speed transistor logic (HSTL) is recently employed. Each of the impedance of the output circuits of the LSI chips and that of the system bus must match with each other, otherwise signals are reflected at the interface to hinder the operation speed of the LSI and prevent the computer system from fully using the intrinsic high-speed performance of the LSI.
It is very important, therefore, to match the impedance of the system bus of the computer system with that of respective output buffers in the output circuits disposed on the LSI chips, which are supposed to be connected to the system bus. Another problem is that the output impedance of semiconductor elements that form the output buffer of the LSI chip varies in response to a change in a system supply voltage, thereby causing an impedance mismatch between the output buffer and the system bus. This raises a necessity of an impedance matching circuit capable of speedily coping with a change in a system supply voltage.
To realize an impedance matching between the output buffer of an LSI chip and a system bus, an effort for standardization of specifications has been conducted by a technology employing an output circuit referred as "a programmable impedance output circuit". In the methodology employing the programmable impedance output circuit, an external resistor whose value is determined depending on requirements by users is connected between "a ZQ-pin" of the LSI package and a system bus held at a low level supply voltage VSS arranged on the system bus. The LSI chip periodically samples and sets the impedance of the output buffer of the LSI chip to an inverse multiple (for example, 1/5) of the impedance of the external resistor.
Even if a system supply voltage varies, the programmable impedance output circuit is expected always to match the impedance of the LSI chip's output buffer with the specific impedance, thereby securing a high-speed interfacing operation between the LSI chip and the system bus.
FIG. 1 shows an equivalent circuit of the programmable impedance output circuit according to a prior art. The external resistor RQ is equivalently represented as being connected between a ZQ-terminal and the low level voltage source VSS, and the resistance of the external resistor RQ is monitored. Practically, the external resistor RQ is connected between the ZQ-pin of the LSI package and VSS of the system board (the system bus held at the low level supply voltage VSS), which is usually a grounding (GND) level system bus of the system board. The ZQ-terminal and the ZQ-pin is connected by a known internal structure of the LSI package, such as bonding wire or wiring bump. A load circuit 11 comprises, for example, a MOS transistor. A resistance ratio between the output impedance of the load circuit 11 and the external resistor RQ determines a potential VZQ at the ZQ-terminal. The potential VZQ is used to detect the resistance of the external resistor RQ.
FIG. 2 shows an example of the structure of the programmable impedance output circuit of the prior art. An impedance matching circuit 81 consists of an external resistance monitor 822 and an A/D converter (dummy buffer) 86 as shown in FIG. 3. The dummy buffer 86 has plural MOS transistors, for example, four MOS transistors 1X, 2X, 4X, and 8X arranged in parallel with one another between a potential VEVAL and the low level voltage source VSS. The MOS transistors 1X to 8X have different gate widths (channel widths) "Ws". More precisely, the gate width W of the MOS transistor 8X is eight (=2.sup.3) times wider than that of the MOS transistor 1X. The gate width W of the MOS transistor 4X is four (=2.sup.2) times wider than that of the MOS transistor 1X. The gate width W of the MOS transistor 2X is two (=2.sup.1) times wider than that of the MOS transistor 1X. Namely, these parallel-connected four MOS transistors provide different on-state resistance R.sub.ON, and therefore different impedance values respectively.
The programmable impedance output circuit of FIG. 2 detects the impedance of the external resistor RQ according to the potential VZQ at the ZQ-terminal and separately controls the ON/OFF states of the MOS transistors 1X to 8X in synchronization with a sampling clock signal, to match the combined impedance of the MOS transistors 1X to 8X with the impedance of the external resistor RQ. Thereafter, the impedance matching circuit 81 matches the combined impedance of the output buffer 82 with the impedance of the external resistor RQ (or an inverse multiple of the impedance of the external resistor RQ).
The load circuit 11 (FIG. 3) consists of a MOS transistor Q1 and resistors R0 and R1. The resistors R0 and R1 have fixed value of resistances respectively, and therefore, the potential VZQ at the ZQ-terminal rises as the external resistance RQ becomes larger and drops as the same becomes smaller.
After the MOS transistor Q1 in the load circuit 11 is turned on, the control circuit 821 sends a set of data consisting of high level "1" and low level "0" as potential values A0 to A3 applied to the respective gate electrodes of the MOS transistors 1X to 8X. Namely, the control circuit 821 separately turns on and off the MOS transistors 1X to 8X to equalize the potential VZQ at the ZQ-terminal to the high potential VEVAL of the dummy buffer 86. According to the set of data A0 to A3 sent from the control circuit 821, the combined impedance of the dummy buffer 86 is matched with the impedance of the external resistor RQ or an inverse multiple of the impedance of the external resistor RQ.
Unlike a resistor, a MOS transistor shows nonlinear characteristics in its triode (ohmic) regime. A drain voltage (drain-source voltage) V.sub.DS of the MOS transistor is dependent on a drain current (drain-source current) I.sub.DS thereof. Namely, a drain voltage V.sub.DS of each of the MOS transistors 1X to 8X varies depending on the value of the external resistor RQ. Even if the control circuit 821 properly sends the set of the data A0 to A3 so that the combined impedance determined by the combination of respective sizes, or the respective gate widths Ws of the MOS transistors may correspond to the external resistor RQ, a drain current I.sub.DS of each of the MOS transistors will deviate from a current flowing through the external resistor RQ if the drain voltage V.sub.DS changes. On the other hand, the impedance of the output buffer 82 is set based on a fixed drain voltage V.sub.DS. Accordingly, the programmable impedance output circuit of the prior art is unable to correctly match the impedance of the external resistor RQ with that of the output buffer 82.
Generally, the programmable impedance output circuit receives a dedicated high level supply voltage VDDQ that is lower than a main high level supply voltage VDD of an LSI chip, to easily realize an impedance matching. The fixed voltage used to define the impedance of the output buffer 82 is usually set to be 1/2 of the dedicated high level supply voltage VDDQ.
Then, even if the impedance of the output buffer 82 is tried to be matched with that of the external resistor RQ, a matching error occurs due to the characteristics of the MOS transistors as mentioned above. FIG. 4 shows a relationship between the drain voltage V.sub.DS and the drain current I.sub.DS of MOS transistors and explains the matching errors due to the I-V characteristics of MOS transistors.
For example, suppose that the impedance of the dummy buffer 86 is defined according to VDDQ/2 with 175.OMEGA..ltoreq.RQ.ltoreq.350.OMEGA., VDDQ=1.5 V at room temperature.
R0 (=R1) is set to make VZQ=VDDQ/2 when RQ=(175+350)/2=263. When RQ=350.OMEGA., VZQ (=V.sub.DS)=0.902 V, and the impedance of the dummy buffer 86 is matched with that of the external resistor RQ by external insertion method.
With respect to the matched MOS transistors of the dummy buffer 86, the actual impedance of the output buffer 82 whose V.sub.DS is defined based on VDDQ/2 deviates from the impedance of the external resistor RQ by +9.3%. Similarly, an impedance error of -10.0% occurs at RQ=175.OMEGA..
In addition to the impedance error due to the I-V characteristics of MOS transistors, there are "size step errors" in the sizes (gate widths Ws) of MOS transistors due to manufacturing errors. These errors make it difficult to keep a product specification error of .+-.10% in the impedance of the output buffer 82.